Design Verification Engineer
Qualifications:
MS or higher degree in EE, CS or related fields,Experience requirements:
Entry level positions:
0-2 years of experienceSenior and above level positions:
a minimum of 2 years of experienceProficiency in System Verilog, Object Oriented Programming, Scripting LanguagesExperience in UVM developmentDetailed understanding of UVM methodology, flows and test-bench structuresBasic understanding of IEEE802.11 PHY and MAC standardExperience in debugging designs of IP level (Wi-Fi Baseband, and MAC) or SOC levelGood communication and documentation skills
Responsibilities:
Work with system architects, algorithm engineers, and RTL designers to define Wi-Fi AP chip verification requirements.Architect and buildIP and system UVM verification environments.Create IP and system verification coverage plans, and generate test cases, based on the specification and review the plan with system architects and design engineersReport failures, participate in the debugging with various teams, and track bugsConduct verification regressions, analyze the results, and review with design teamsDevelop verification flows for code coverage and functional coverage for Baseband, MAC, and SOC Recommended Skills Algorithms Debugging Object Oriented Software Development Scripting System Verilog Communication Apply to this job. Think you're the perfect candidate? Apply on company site $(document).ready( function() $(#ads-desktop-placeholder).html(
n
n
n Estimated Salary: $20 to $28 per hour based on qualifications.
|
|
 | |
