CAD Engineer
Company Name:
Career Development Partners
At least 3 years of experience writing DRC, LVS and ERC verification rule decks for BiCMOS, Bipolar and CMOS processes.
Knowledge of front-to-back custom IC design flow.
Verification/Extraction/Layout CAD support experience. Relevant experience includes Assura, Virtuoso Composer, Layout, QRC, IC Validator.
Knowledge of shell and scripting languages (Skill, Perl, Bash).
Actual layout design experience is very helpful.
Knowledge of IC simulation tools like HSPICE, SPECTRE is a plus.
Demonstrate knowledge of parasitic extraction flows.
Demonstrate experience in developing, installing and maintaining foundry PDKs.
Possess working knowledge of version control systems like SVN.
Must possess excellent communication and interpersonal skills.
Detail oriented, well organized and a team player.
B.S. or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience).
Required Skills
Develop, maintain and support physical verification rule decks for BiCMOS, Bipolar and CMOS processes.
Develop Skill, and Shell routines to integrate, automate, and maintain IC layout design flow.
Help setup, configure, and support layout and verification tools (Virtuoso, Assura, IC Validator, etc.).
Assist mask design groups on layout and verification issues.
Write detailed documentation for all development and implementation work in a manner that provides for knowledge transition to other resources and a guide for on-going support.
Evaluate 3rd party CAD tool releases. Integrate them into existing layout environment, as needed.
Estimated Salary: $20 to $28 per hour based on qualifications.
Career Development Partners
At least 3 years of experience writing DRC, LVS and ERC verification rule decks for BiCMOS, Bipolar and CMOS processes.
Knowledge of front-to-back custom IC design flow.
Verification/Extraction/Layout CAD support experience. Relevant experience includes Assura, Virtuoso Composer, Layout, QRC, IC Validator.
Knowledge of shell and scripting languages (Skill, Perl, Bash).
Actual layout design experience is very helpful.
Knowledge of IC simulation tools like HSPICE, SPECTRE is a plus.
Demonstrate knowledge of parasitic extraction flows.
Demonstrate experience in developing, installing and maintaining foundry PDKs.
Possess working knowledge of version control systems like SVN.
Must possess excellent communication and interpersonal skills.
Detail oriented, well organized and a team player.
B.S. or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience).
Required Skills
Develop, maintain and support physical verification rule decks for BiCMOS, Bipolar and CMOS processes.
Develop Skill, and Shell routines to integrate, automate, and maintain IC layout design flow.
Help setup, configure, and support layout and verification tools (Virtuoso, Assura, IC Validator, etc.).
Assist mask design groups on layout and verification issues.
Write detailed documentation for all development and implementation work in a manner that provides for knowledge transition to other resources and a guide for on-going support.
Evaluate 3rd party CAD tool releases. Integrate them into existing layout environment, as needed.
Estimated Salary: $20 to $28 per hour based on qualifications.
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