Senior Mask Design Engineers
SanDisk Corporation needs Senior Mask Design Engineers in Milpitas, California to work as part of physical design team, design engineer, layout manager and layout project lead to perform memory technology layout design. Focus on charge pump and voltage generator utilizing analog layout and analog layout placement matching and routing. Apply and evaluate parasitic and its impact to layout, optimize critical paths, lead test chip project and co-lead derivate project. Develop cell-level, block-level and full chip level DRC/LVS and perform manual routing and semi-auto routing. Responsible for the optimization of various blocks including routing and via optimization, full chip activities including tape-out and ECOs after initial tape-out, test structure development including structures necessary for design rule development, and I/O circuits layout, ESD circuits layout, and pad layout. Apply layout and schematic hierarchy of existing chips to make changes to existing chips and take ownership of parts of the full chip. Develop floor plan to optimize block placement and routing.
Employer will accept Bachelors degree in Electrical Engineering, Engineering or related technical field, followed by 6 years of progressive, post-baccalaureate work experience in job offered or in a design engineer-related occupation. Experience must include:
1. Designing memory technology;
2. Designing layout sense amplifier, control circuit, ECC, power supply circuit, decoder circuit in development of memory technology;
3. Layout standard cell library;
4. Developing cell-level, block-level layout and analog layout matching and routing;
5. Developing memory, pitch layout;
6. Supporting optimization of various blocks including routing and via optimization;
7. Test chip and product chip layout and integration;
8. I/O layout circuits, ESD layout circuits, LVS/DRC, Cadence VLE, VSL, CCAR, PCELL;
9. Hercules, Calibre, DRC and LVS verification tools; and
10. Unix.
To apply, please reference job code #SD167 when mailing resume to:
SanDisk Corporation
951 SanDisk Drive
MS: HRGM
Milpitas, CA 95035Estimated Salary: $20 to $28 per hour based on qualifications.
Employer will accept Bachelors degree in Electrical Engineering, Engineering or related technical field, followed by 6 years of progressive, post-baccalaureate work experience in job offered or in a design engineer-related occupation. Experience must include:
1. Designing memory technology;
2. Designing layout sense amplifier, control circuit, ECC, power supply circuit, decoder circuit in development of memory technology;
3. Layout standard cell library;
4. Developing cell-level, block-level layout and analog layout matching and routing;
5. Developing memory, pitch layout;
6. Supporting optimization of various blocks including routing and via optimization;
7. Test chip and product chip layout and integration;
8. I/O layout circuits, ESD layout circuits, LVS/DRC, Cadence VLE, VSL, CCAR, PCELL;
9. Hercules, Calibre, DRC and LVS verification tools; and
10. Unix.
To apply, please reference job code #SD167 when mailing resume to:
SanDisk Corporation
951 SanDisk Drive
MS: HRGM
Milpitas, CA 95035Estimated Salary: $20 to $28 per hour based on qualifications.
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