ASIC Design Engineer

KUMAR, SAILESH KUMAR


213-519-2814 | saileshk@usc.edu | www.linkedin.com/in/saileshk | www.github.com/sailesh-kumar 


120 Newbury Street, Milpitas, CA 95035


 


SUMMARY           Recently graduated M.S. in Electrical Engineering from USC, specializing in VLSI looking for opportunities in Digital Hardware/FPGA/ASIC/SoC – Design, Verification, and Testing


                            


RELEVANT          Directed Research Assistant, USC                                                                      Jan 2016 – July 2016                        


EXPERIENCE     •     Implemented a matrix completion algorithm in Verilog



  • Design involved parameterized matrix multiply, normalization, and gradient descent modules

  • Execution units used were floating point modules

  • Achieved precision of up to 10 decimal places

  • Coded a pre-processor, in C++, to convert decimals to IEEE floating format used as input


                              •     Prepared a simple tutorial to use MATLAB ­– StateFlow


                              •     Secured and facilitated the access to a data set repository for a research analysis


Course Grader – Computer Systems Organization, USC                                      Aug 2015 – Dec 2015   Graded homework and exams; held office hours to guide students


                              Project Trainee – Indian Institute of Science                                                       Jan 2014 – July 2014


                              Implemented maximum power point tracking algorithm for a solar power supply


 


EDUCATION       University of Southern California


Master of Science, Electrical Engineering – VLSI (3.53/4)                                                      Aug 2016          


 


Bangalore Institute of Technology


Bachelor of Engineering, Electrical & Electronics (83.1/100 - ranked among top 1%)                July 2014


 


PROJECTS           Simple Chip Multi-Processor (Verilog, NCSim, Design Compiler, PrimeTime, Encounter, Conformal)



  • Designed a 4 node ring router with 64-bit 4 stage variable width processor and network controllers

  • Synthesized with timing & formal equivalence check; placed & routed (partitioning-floorplanning)

  • Simulation carried out at every design step with testbenches written

  • Achieved one of the best designs in class by adopting the right balance between area and delay


General Purpose Pipelined Processor (Virtuoso, Perl)



  • Designed the schematic and layout for a simple 5 stage pipelined processor involving SRAM

  • Accomplished clock gating for power minimization and logical effort for delay minimization

  • Used dynamic flipflops and made modifications to enable 32-bit data storage in 16-bit SRAM

  • Verified results using Perl


Tomasulo Processor Implementation – (VHDL, ModelSim, Xilinx – ISE)



  • Designed with Branch Prediction, Store Word Buffer, and Free Register List units on FPGA

  • Employed Copy-Free Checkpointing for effective utilization of FPGA resources


16-bit 5 Stage Pipelined Processor – (Verilog, ModelSim)



  • Built 16-bit 5 stage pipeline and analyzed timing

  • Increased throughput by adding forwarding and early branching


FIFO Design and Clock Domain Crossing (CDC) – (VHDL, ModelSim)



  • Designed a one-clock and two-clock FIFO

  • Conceived a RAM based FIFO with input & output registers to emulate a practical realization


Computer Architecture Projects – (VHDL, Xilinx ­­– ISE, Verilog, NCSim, Design Compiler)



  • Designed fully-associative Content Addressable Memory with Least Recently Used policy on FPGA

  • Implemented and synthesized a simplified single precision floating point multiplier

  • Analyzed static latch based pipeline for time­-stealing and borrowing cases with wave pipelining


Automatic Test Pattern Generator and Fault Simulator for Combinational Circuits – (C language)



  • Implemented PODEM based ATPG module to generate test vectors for combinational circuits

  • Designed Parallel and Deductive fault simulators and used them to detect actual faults


Programming Projects (Java, C++)



  • Coded Bulgarian Solitaire, Maze route finder, Random text generator, and a Concordance program


                                                                                                               


SKILLS                  Coding Languages: Verilog, VHDL, Perl, C, C++, Java


Tools: Simulation: Mentor Graphics – ModelSim, Cadence – NCSim, Synopsys – HSPICE


Synthesis: Synopsys Design Compiler         Static Timing Analysis: Synopsys – PrimeTime


Place and Route: Cadence – Encounter          Logical Equivalence Checker: Cadence – Conformal


FPGA Design Suite: Xilinx ISE                     Layout Suite: Cadence – Virtuoso


 

  • ID#: 108393
  • Location: Milpitas, CA , 95035

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