ASIC Design Engineer

Preetham Bobde Chikyala

Contact No.: 4087089662




Career Objective

To obtain a position that will enable me to apply and utilize my technical skills and experience effectively, and to achieve a fruitful career along with the growth of the organization.


Work Experience

  • Worked as an Engineer in Design at Qualcomm India Private Limited, Bangalore from Sep 3rd 2012 to Oct 31st 2012 (2 months).
  • Worked as an ASIC Design Engineer at Marvell India Private Limited, Bangalore from June 14th 2010 to Aug 31st 2012 (2 year 3 months).
  • Worked as a Design Engineer Intern at Vitesse semiconductors, Hyderabad from Jan 11th 2010 to June 7th 2010 (6 months).



Master of Technology, from International Institute of Information Technology Hyderabad, in the field of ‘VLSI & Embedded Systems’, during the year 2008 – 2010 with the CGPA of 9.03/10.



  • Ø Summary
    • 3 years of work experience as ASIC Design Engineer.
    • Have RTL Design and integration experience in 28nm and very high speed ASIC Designs in 2 tapeouts.
    • Have experience in verification, synthesis, formal verification, STA all using synopsys tools (VCS, DC, Formality and PT) and CDC (Clock Domain Crossing) check using 0in.
    • Also have brief knowledge and experience of FPGA validation.
    • Have hands on experience and knowledge in pipelined processor architecture.


  • Ø RTL Design and Integration
    • Designed IP’s from spec to RTL (ex: Display port and HDCP)
    • Developed RTL to enhance features in the existing blocks internal to the organization
    • Integrated few internal and third party IP’s like USB2.0 (Host and OTG), temperature sensor, I2C, SPI and PCIe into SoC.


  • Ø Verification
    • Developed test bench to verify the RTL using VCS before releasing it to verification team.
    • Worked very close with the verification team in debugging the issues using verdi.
    • Also generated test cases for complete verification of the module with the help of verification team in System Verilog and UVM.


  • Static Timing Analysis Using Prime Time
    • Have experience working in timing closure of two multi-clock, multi voltage modules to signoff.
    • Developed many scripts using Perl, Tcl and Awk to automate and to optimize the generation of timing ECO’s.
    • Also took part in creating SDC files for STA.



Technical Skills

  • HDLs                                   : Verilog, VHDL
  • EDA tools                            :  VCS, Design Compiler, Prime Time, Verdi
  • Programming Languages     :  C & Data structures
  • Scripting Languages            :  AWK, Perl
  • Operating Systems               :  Linux, UNIX, windows
  • Specifications                      :  DisplayPort, I2C, USB2.0, AHB, AXI, HDCP




System Verilog, OVM, UVM, C++, Tcl, Formality, ISE, 0in (for cdc check), HDMI,  DDR, USB3.0, HDCP2.0,  PCIe , DFT and Encryption techniques - RSA, SHA128, AES.



Achievements and Extra Curricular Activities

  • Have been rewarded for working “above expectations” at Marvell.
  • Received the honor of “Dean’s list of Academic Awards”, for the outstanding academic performance in the year 2009 and 2010 during my Masters at IIITH.
  • Secured All India Rank (AIR) 862 with a percentile of 96.90 in GATE 2008.
  • Participated and won many Singing and Painting competitions held in our college and school.



I hereby declare that all the information mentioned above is true to the best of my knowledge.




Preetham Bobde Chikyala


  • ID#: 66093
  • Location: Milpitas, CA , 95035

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